مهندسی برق الکترونیک
مدیر وبلاگ : الینا علیزاده
PHASE-LOCKED loops (PLLs) and delay-locked loops (DLLs) are extensively used in microprocessors and digital signal processors for clock generation and as frequency synthesizers in RF communication systems for clock extraction and generation of a low-phase-noise local oscillator signal from an on-chip voltage-controlled oscillator (VCO) which might have a higher open-loop noise performance. The basic block diagram of a PLL is shown in Fig. 1. The phase of a local VCO signal is compared with the phase of a (hopefully) low-noise reference signal and the difference of the two phases is low-pass filtered and applied to the controlling node of the VCO. If the input signal frequency is within the VCO tuning range, the
VCO output is also “locked” to the same frequency as the input signal and the phase difference between the two signals is very small. In RF communication systems, frequency synthesizer noise directly degrades the overall noise performance of thesystem. Similarly, timing jitter in PLLS of high-performance processors degrades the timing margins of the overall design. Hence, the accurate prediction of PLL noise performance is critical for the design of these systems. Noise generation mechanismsforPLLsandDLLsarevery different. InaDLL,thevoltagenoisefromeachofthedelaystagesaccumulates for one period of the input reference signal and then thehand, in a PLL, aVCOis present in the feedback loop and the difference in the phase of the reference and theVCOsignal is filtered and used as the control signal of the VCO. Therefore, one of the noise sources of the VCO is the difference of the phase noise of the reference signal and the VCO output along with the noise in the loop filter, phase detector, and frequency dividers. This paper addresses the problem of noise analysis of PLLs. The starting point of this work is – where noise analysis of open-loop oscillators based on a novel perturbation analysis of an oscillatory system of equations was presented. However, the PLL is a phase feedback system and special techniques are required for solving the associated system of equations. In this work, a system of stochastic differential equations governing the behavior of the PLL VCO phase are developed. The PLL is assumed to be locked to a reference periodic signal which is assumed to have Brownian motion phase deviation. It is shown in Section III that the PLL output phase, in locked condition, is a sum of two stochastic processes: the Brownian motion phase deviation of the reference signal and one component of an appropriate multidimensional Ornstein–Uhlenbeck process. Similar to  and , it is shown that the PLL output is asymptotically wide-sense stationary. Using the statistics of the phase deviation process, a general expression for the power spectral density (PSD) of the PLL output is obtained. This expression is used to derive the PSD of the PLL output for some specific loop filter configurations in Section IV. From the output spectrum, it can be observed that that the PLL output PSD closely follow the reference signal spectrum for very small offset frequencies and follows the open-loop VCO output spectrum for high offset frequencies. This fact has been experimentally observed and widely reported in the literature. Finally, experimental results on an example circuit are presented in Section V. output phase is aligned with the input signal phase.
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شنبه 18 شهریور 1396 05:19 ب.ظ
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